PCB Supplier

Package-on-Package

CPU on DRAM, stacked in one reflow.

Package-on-Package assembly for mobile, wearable and SiP designs where every square millimeter counts. Flux-dip jet, single-pass reflow, 3D X-ray per stack.

BGA pitch
0.3 mm
Stacks
X-ray
100%
Reflow
1 pass
Min pitch
0.3 mm
Tiers
2 / 3

Process sequence

One reflow, every tier landed

Bottom-tier paste print → tier-2 flux dip → tier-3 flux dip → single reflow — no intermediate thermal cycles to stress the underfill.

STEP 1
Paste print

Laser-cut stencil · bottom-tier pads only

STEP 2
AP placement

0.4 mm pitch FCBGA, placed first

STEP 3
Flux dip T2

DRAM balls dipped in flux jet, not paste

STEP 4
Flux dip T3

Top-tier µBGA dipped and placed

STEP 5
Reflow + X-ray

Single profile cures entire stack · 100% 3D X-ray

Why choose PoP

When board area runs out, build up

PoP keeps interconnect between CPU and memory short — better signal integrity, lower power — while freeing up board area for sensors, RF and batteries.

  • Phones & wearables
  • AR / VR headsets
  • IoT edge compute
  • Drone flight controllers
  • Smart watches
  • Automotive infotainment
  • Industrial AI modules
  • Medical wearables

Capability

Published PoP capability

PoP Assembly — Specification
Geometry
Tiers2-tier · 3-tier (standard)
Min pitch (top tier)0.3 mm
Min pitch (bottom tier)0.4 mm
Min stack height1.2 mm typical · 0.9 mm ultra-thin
Max die size (top)15 × 15 mm
Process
Flux methodDEK flux-dip jet · controlled depth
Reflow10-zone · N₂-optional profile
UnderfillOptional capillary or NCF
Inspection
X-ray100% 3D X-ray · Nordson Dage Quadra 7
AOIPre-reflow paste AOI + post-reflow optical
Cross-sectionOn sample lots per program
Board support
Board thickness0.4 – 3.2 mm
Min board flatness≤ 0.75% warpage (IPC-TM-650 2.4.22)
Compliance
QualityIPC-A-610 Class 3 · J-STD-001
CertISO 9001 · IATF 16949 · ISO 13485

Frequently Asked Questions

Package-on-Package FAQ

Ask a specialist
01Can you do PoP on a 4-layer board?

Not recommended — PoP needs short BGA escape routing to work. For production we ask for ≥ 8 layers with HDI or stacked microvias under the AP site.

02How do you handle reworkability?

PoP is reworkable but difficult — we budget 3-4 hours per stack for rework with a localized thermal zone. We prefer to de-risk up-front with a signoff build & full X-ray.

03Do you underfill every stack?

Not by default. For consumer electronics we ship non-underfilled; for drop-sensitive products (wearables, automotive) we add capillary or NCF underfill as a spec option.

04What about warpage control?

PoP is the first assembly process to punish a warped board. We pre-screen incoming boards to ≤ 0.75% warpage per IPC-TM-650 2.4.22 and use dedicated support jigs during reflow.

Ready when you are

Send your Gerber & BOM — get a quote in 24 hours.

NDA available · Free DFM review · Senior engineer response.